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The storage abstraction layer is initialized which is used to load further bootloader images.Some systems have a separate System Control Processor (SCP) for power, clock, reset and system control.The cold boot path is mainly executed by the primary CPU, other than essential CPU initialization executed by all CPUs.The secondary CPUs are kept in a safe platform-specific state until the primary CPU has performed enough initialization to boot them.BL1 also initializes UART0 (PL011 console), which enables access to the BL1 loads and passes control to BL2 at Secure-EL1.

Platform security is initialized to allow access to controlled components.A platform defined base address is used to specify the load address for the BL3-1 image.It also defines the extents of memory available for use by the BL3-2 image.In the case of a warm boot, a CPU is expected to continue execution from a seperate entrypoint.In the case of a cold boot, the secondary CPUs are placed in a safe platform-specific state (see the BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from the CCI-400 slave interface corresponding to the cluster that includes the primary CPU.BL2 copies the information regarding the trusted SRAM populated by BL1 using a platform-specific mechanism.It calculates the limits of DRAM (main memory) to determine whether there is enough space to load the BL3-3 image.The ARM Trusted Firmware implements a subset of the Trusted Board Boot Requirements (TBBR) Platform Design Document (PDD) [1] for ARM reference platforms.The TBB sequence starts when the platform is powered on and runs up to the stage where it hands-off control to firmware running in the normal world in DRAM. The ARM Trusted Firmware also implements the Power State Coordination Interface (PSCI) PDD [2] as a runtime service.PSCI is the interface from normal world software to firmware implementing power management use-cases (for example, secondary CPU boot, hotplug and idle).Normal world software can access ARM Trusted Firmware runtime services via the ARM SMC (Secure Monitor Call) instruction.

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  3. ProblemAbstract DB2 10.5 APAR Fix list contains list of APARs shipped for each fix pack in DB2 Version 10.5 for Linux, UNIX and Windows products.

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